When processing dimension of a MOSLSI is reduced and gate length is shortened, an operating voltage of MOS transistor becomes smaller accordingly. Power source voltage of a MOSLSI of 65 nm processing generation which is expected to be mass-produced within a year or two years is reduced to approximately 1V. Moreover, a operation speed of an LSI has been attained more higher speed in every generation. However, in a floating gate type or multi-layered insulation films type semiconductor nonvolatile memory, it is difficult to reduce the writing voltage or erasing voltage thereof and it is also difficult to improve writing speed only by reduction of the gate length.
This is because in the case of a semiconductor nonvolatile memory having a floating gate, it is difficult to reduce a thickness of an insulation film provided between the floating gate and a channel surface with guaranteeing retention of memory. In the case of the multi-layered insulation films type semiconductor nonvolatile memory, a thickness of a tunnel insulation film between a memory site for charge storage and a channel surface cannot be reduced.
Therefore, the writing voltage in a NAND type flash memory is still approximately 17V and this is significantly high when compared to approximately 1V of power supply voltage of the MOS logic (refer to FIGS. 8 and 9 of Non-Patent-Document 1).
For the improvement of effective memory density of the nonvolatile memory, a technology to store in one memory cell multiple values which are more than two values of “1” and “0”, so-called a multi-level memory, has been developed. However, because in this memory, a value of electric parameters such as floating gate potential, charge stored in the multiple insulation layer and gate threshold voltage, that continuously changes according to writing time and writing voltage, is splitted into multi-level by some control, it is difficult to clearly write between multi-level and to keep the each level separated without setting a large interval between each level.    Patent Document 1; Japanese Patent Laid Open Application, JP S58-23483 A;    Non-Patent-Document 1; Y. Shin et al., “A Novel NAND-type MONOS Memory using 63 nm Process Technology for Multi-Gigabit Flash EEPROMs”, session 13-6, 2005 IEDM Technical Digest, pp. 337-340, December, 2005